In the field of semiconductor device manufacturing, active semiconductor devices such as, for example, transistors are normally manufactured or fabricated by well-known front end of line (FEOL) technologies. Following the formation of active semiconductor devices such as transistors, stresses are normally induced into channel regions of the transistors through, for example, applying stress liners to improve performance. As is known in the art, in certain applications the stress liners may also function as etch-stop layers during a subsequent contact formation process.
A semiconductor chip or semiconductor structure may include different types of transistors. A transistor may be a field-effect-transistor (FET) such as, for example, a complementary metal-oxide-semiconductor (CMOS) FET, and may be the type of either a p-doped FET (PFET) or an n-doped FET (NFET). Different types of transistors may be manufactured on a same substrate of a semiconductor chip or structure.
As is well-known in the art, a compressive stress liner is normally applied to a PFET transistor and a tensile stress liner is normally applied to an NFET transistor. Both stress liners may be formed by a conventional dual stress liner (DSL) process. However, the conventional DSL process may create a transitional region or area, as shown in FIG. 1 below, where the two different types of liners overlap.
FIG. 1 is a simplified illustration of a dual stress liner formed by following a conventional DSL process. A semiconductor chip or semiconductor structure 10 may have two device regions 11 and 12 wherein two different types of transistors maybe manufactured. A first type of stress liner 21 may be formed to cover transistors in device region 11, and a second type of stress liner 23 may be formed to cover transistors in device region 12. Stress liners 21 and 23, which together forms the dual stress liner, may be nitride stress liners and may be compressive and/or tensile stress liners. Stress liner 21 may be covered by an oxide layer 22. In a transitional region or area 20, as is illustrated in FIG. 1, a portion of stress liner 21 and oxide layer 22 may be covered by stress liner 23. Transitional region 20 may form a tri-layer stack of nitride/oxide/nitride material, with a thickness that is thicker than either stress liner 21 or stress liner 23.
As is known in the art, differences in structure, as well in thickness, between the tri-layer stack of nitride/oxide/nitride in transitional region 20 and the single stress liners in device regions 11 and/or 12 may complicate an etching process in forming electric contacts for semiconductor structure 10. For example, when contacts of proper depth are formed through a single stress liner in a device region, contacts formed in transitional region 20 may not have sufficient depth, due to under-etching of the stack of nitride/oxide/nitride, to reach areas underneath that the contacts are intended for. On the other hand, creating contacts by etching through the stack of nitride/oxide/nitride in transitional region 20 may cause punch-through of contacts in gate, source, and/or drain areas of devices in a device region.
Therefore, there exists a need in the art to broaden the process window of forming contacts by minimizing, removing, and/or eliminating the stress liner overlap in transitional region 20 caused by a conventional DSL process. In other words, there is a need to tailor the structure and thickness of a dual stress liner in transitional region 20, where two different types of stress liners conjoins, such that a process of forming contacts for a semiconductor structure may be significantly simplified. In addition, there is also a need to simplify the current process of forming a dual stress liner.
It will be appreciated that for the purpose of simplicity and clarity of illustration, elements in the drawings have not necessarily been drawn to scale. For example, dimensions of some of the elements may be exaggerated relative to other elements for clarity purpose.